SLVCONTINUE=NO_EFFECT, AUTOMATCHREAD=I2C_WRITE, AUTOACK=NORMAL, SLVNACK=NO_EFFECT, SLVDMA=DISABLED
Slave control register.
| SLVCONTINUE | Slave Continue. 0 (NO_EFFECT): No effect. 1 (CONTINUE): Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. |
| SLVNACK | Slave NACK. 0 (NO_EFFECT): No effect. 1 (NACK): NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). |
| SLVDMA | Slave DMA enable. 0 (DISABLED): Disabled. No DMA requests are issued for Slave mode operation. 1 (ENABLED): Enabled. DMA requests are issued for I2C slave data transmission and reception. |
| AUTOACK | Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. 0 (NORMAL): Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). 1 (AUTOMATIC_ACK): A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. |
| AUTOMATCHREAD | When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. 0 (I2C_WRITE): The expected next operation in Automatic Mode is an I2C write. 1 (I2C_READ): The expected next operation in Automatic Mode is an I2C read. |